An access-transistor-free (0T/1R) non-volatile resistance random access memory (RRAM) having a cross point architecture has been described by Yi-Chou Chen et al., “An Access-Transistor-Free (0T/1R) Non-Volatile Resistance Random Access Memory (RRAM) Using a Novel Threshold Switching, Self-Rectifying Chalcogenide Device,” IEEE International Electron Devices Meeting 2003. The described prior art device 10 shown in FIG. 1A includes a cross point array with the bit lines 20 and word lines 21 arranged perpendicularly. Each memory cell 11 has a top electrode 12 and bottom electrode 13 (TiW) and a chalcogenide layer 14 (Ge2Sb2Te5) therebetween. The operation of the device 10 requires that the chalcogenide layer 14 remain amorphous.
During operation of the device 10, memory is retained via the modulation of the electronic switching threshold voltage. Any semiconductor layer that experiences a field-assisted carrier-concentration dependent generation mechanism and a competitive tarp-assisted carrier recombination will show electronic switching. The threshold voltage is the point at which the generation rate exceeds the recombination rate. At this point, the amorphous material experiences snapback, and the resistance falls, as shown in FIG. 1B. The modulation of this phenomenon is critical to the device's 10 operation.
The threshold voltage for electronic switching can be modulated by controlling the occupancy state of recombination centers. It has been shown that the threshold voltage of a recently amorphized germanium-antimony-tellurium (GST) material increases in time. Agostino Pirovano, et al., “Low-Field Amorphous State Resistance and Threshold Voltage Drift in Chalcogenide Materials,” IEEE Transactions of Electron Devices, vol. 51, no. 5, May 2004. This can be explained by empty acceptor-like traps that exist immediately after the material becomes amorphous. Over time, the traps fill, resulting in an increased Fermi level.
The threshold voltage of the device 10 is changed by applying differing electronic potentials to modulate the trap states. To create a low threshold voltage, a lower bias that is greater than the threshold voltage is applied to the chalcogenide layer 14. Since the bias exceeds the threshold voltage, the generation rate exceeds the recombination rate and free carriers exist for conduction. At the same time, the acceptor-like traps empty as the holes tunnel out of the traps. Since it takes time for the traps to fill with holes, excess holes exist for conduction. While the traps remain empty, the threshold voltage remains low.
To increase the threshold voltage, the applied bias is increased resulting in filled traps. If a bias is applied that exceeds the bias used for creating the low threshold voltage, a higher electric field in the chalcogenide layer 14 will result. This field will allow for trap-assisted tunneling. The “hole” occupying the acceptor-like trap will tunnel out since its barrier will have been reduced by the high electric field. This creates a higher threshold voltage.
There are two significant problems with the FIG. 1A device 10: 1) the need for an amorphous material and 2) poor data retention. Since the modulation of the threshold voltage relies upon electronic switching of an amorphous material, it is critical that the material remain amorphous. If the chalcogenide layer 14 crystallizes there will be no electronic switching effect. Since many chalcogenide materials will crystallize at temperatures below what devices are subjected to during manufacturing processes it is a problem to keep the materials amorphous. For example, many chalcogenide materials will crystallize at temperatures below about 265° C., which is the surface mount technology reflow oven peak temperature, an oven used in the manufacture of memory devices. In addition, the device 10 shows a data retention of only 5000 seconds at room temperature.
It would be desirable to have an access-transistor-free memory device that could be subjected to higher temperatures and has improved data retention.